1. Field of the Invention
The present invention relates to an arithmetic circuit for calculating the absolute value of the difference between a pair of input signals. More specifically, the present invention relates to a processor which can calculate the absolute difference between a pair of input digital signals at a high speed without needing additional elements.
2. Description of the Prior Art
One important operation in digital signal processings such as digital video signal processings and digital audio signal processings is to calculate the absolute value of the difference between a pair of digital signals. For example, in automatic equalizer system for removing transmission path distortion, if a so-called zero forcing algorithm is used, it is necessary to calculate the absolute value of the difference or error between an input signal and an output signal of the automatic equalizer and to introduce a weighting coefficient which will minimize the above absolute value of difference. In such a signal processing, a real time operation is required, and therefore, a high speed operation is very significant.
Heretofore, an arithmetic circuit for calculating the absolute value of the difference between a couple of input signals A and B, i.e., .vertline.A-B.vertline. has included one subtracter receiving the two input signals A and B to output a difference C=(A-B). Further, a sign inverting circuit is provided to receive the difference C so as to discriminate whether the sign of the difference C is positive (+) or negative (-). If the difference C is positive, the sign inverting circuit outputs the difference C without inversion as its output signal D. On the other hand, if the difference C is negative, the sign inverting circuit operates to invert the sign of the difference C. Namely, -=(B-A) is outputted as the output D. Thus, the output D of the sign inverting circuit is indicative of .vertline.A-B.vertline..
In the above arithmetic circuit, the sign inverting circuit is ordinarily constituted of another subtracter which executes the operation of (0-C) when the C is negative. Therefore, the arithmetic circuit is composed of two cascade-connected subtracters, and therefore, inevitably needs a long time of operation.
Further, the recent signal processing has been executed by using microcomputers, microprocessors, etc. In such a case, the above mentioned calculation for the absolute value of the difference is performed by means of an arithmetic and logic unit (abbreviated "ALU" hereinafter) which the most important part of microcomputers and microprocessors. The ALU is supplied with a couple of input signals in the form of two's complement, because the two's complement is easy to indicate the positive and the negative of numerical values in the arithmetic operation and also because it allows an adder and a subtracter to be formed by very similar circuits. Further, the ALU is operated by a control signal to selectively an arithmetic operation of the four fundamental rules and a logical operation. Namely, the ALU performs a selected one among addition, subtraction, multiplication, division, logical sum (OR), logical product (AND), exclusive OR, etc. However, the ALU does not have the function of absolute value calculation.
In the conventional signal processors using the microcomputer or the microprocessor, therefore, the output of the ALU is supplied to a sign inverting circuit. As mentioned hereinbefore, this sign inverting circuit is a subtracter, and therefore, the cascade of the ALU and the subtracter will also inevitably need a long time of operation for the absolute value of difference. Accordingly, this operation of the absolute value is one hindrance in the speed up of the digital signal processor intended to execute the real time signal processing of input signals.
As one measure for speeding up the signal processing, it is considered to apply a so-called pipeline architecture to the ALU and the associated sign inverting circuit. Namely, the ALU and the sign inverting circuit are driven with two different trains of clocks, respectively, so that the time of the absolute value calculation is determined by only the operation time of either the ALU or the sign inverting circuit (subtracter). As a consequence, the operation will be substantially speeded up. To the contrary, an external instruction will be divided into two instructions. This will result in increase of the number of required instructions and complication of instructions per se.
Furthermore, with the latest large-scaled inclination of microcomputers and microprocessors, there is increased the possibility of noises generating in wirings and elements of the circuit because of variation of the supply voltage and electrostatic coupling. The noises will be a cause for mulfunction of the circuit. Therefore, in order to find out and correct malfunction, there has been proposed and already actually reduced in practice to provide a sub-ALU and a comparator in addition to a main ALU, so that the two ALUs simultaneously executes the same operation, and the results of the operation are compared by the comparator. If the outputs of the two ALUs are not the same, the same operation is repeated until the outputs of the two ALUs become the same.
This arrangement can surely decrease the error of the operation, but although two ALUs and one comparator are provided, the function of the ALU itself is not expanded at all. Namely, the ALU per se cannot still perform the absolute value calculation of the difference.